The higher clock frequencies and smaller geometry sizes in today's integrated circuits have led to an increase in speed related defects which are commonly referred as transition delay faults. Thus, it is desirable that the devices are screened for such faults using at-speed testing. Effective scan-based at-speed test techniques are available in leading automated test pattern generator (ATPG) tools. The most common at-speed tests to check for manufacturing defects and process variations include test patterns created for the transition and path-delay fault models.
While creating at-speed test patterns, it is desirable to account for timing exceptions and constraints such as false and multi-cycle paths. If these paths are not handled correctly during scan-based at-speed test pattern generation, it can lead to lower test quality by failing otherwise passing chips on the tester which reduces product yield. False Paths are those timing arcs in design where changes in source registers are not expected to be captured by the destination register within a particular time interval. False Paths can be categorized under various design topologies such as a) static false path—timing arc in design where excitation of source register will not have any impact or change in destination register, b) False reset timing arc, or c) asynchronous false path (e.g., core data register (CDC) Path)—where clock domain of the source register is asynchronous to the clock domain of the destination register and then the path is considered as asynchronous. A multi-cycle path in a sequential circuit is a combinational path which does not have to complete the propagation of the signals along the path within one clock cycle. For a multi-cycle path of N, a given design should ensure the signal transition propagated from source to destination occurs within N clock cycles.
Typically a false path in a circuit is not activated because of the circuit functionality and delay values of the circuit components. However, a scan-in operation during scan-based at-speed test can load in nonfunctional states, which may sensitize these paths. Such patterns may eventually fail on silicon as these paths are not timing closed in station. This may cause a passing chip to be branded as a defective chip and hence resulting in yield loss.
In order to avoid such scenario, the source of a false/multi-cycle path can be marked as a dynamic ‘X’ (unknown value) source in the ATPG. In case of designs using scan compression, the ATPG coverage can be severely degraded in the presence of increased density ‘X’ sources and it could potentially impact the effective achievable compression. The X-sources can limit both unload compression by masking observation, and the load compression by requiring additional care bits to prevent Xs or avoid their effect on unload data. Failure in effective handling of X-sources might impact the observability of the other non-X scan cells and can potentially inflict lower test coverage and increase in pattern count.